1. Field of the Invention
The present invention relates generally to electrically programmable and erasable memory and, more particularly, to methods for easing the buried contact induced operation and increasing the reliability window of a nitride trapping memory.
2. Description of Related Art
Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a nonvolatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names charge trapping memory, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Charge trapping memory devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of a charge trapping flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology continues to scale down.
A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The substrate includes a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
A traditional floating gate device stores 1 bit of charge in a conductive floating gate. The advent of charge trapping memory cells in which each charge trapping memory cell provides 2 bits of flash cells that store charge in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of a charge trapping memory memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in floating gate devices. The charge in the ONO dielectric with a nitride layer may be either trapped on the left side or the right side of a charge trapping memory cell.
A frequently used technique to program charge trapping memory cells in a charge trapping memory array is the hot electron injection method. During an erase operation, a common technique used to erase memory cells is called the band-to-band tunneling hot hole injection technique, where the eraseability is highly dependent on the lateral electric field. The other side potential, from the side that is being erased, of a charge trapping memory cell, is likely to have a lateral electric field effect on the eraseability. Evaluating the endurance and retention of a charge trapping memory array, the lack of uniformity in eraseability causes a margin loss due to cycling and baking. The other side of charge trapping memory cells are left floating (or connected to ground) and may be coupled to an uncertain voltage level (e.g. 1 volt or 4 volts), which causes a variation of the erase threshold of array cells. This in turn causes Vt distribution to be wider after an erase operation.
In a conventional program algorithm of a flash memory, a channel hot electron program is applied to the flash memory with a program voltage. The flash memory is then program verified by a program verify voltage. Such an algorithm produces a significant loading induced voltage threshold differential between flash memory cells. The retention loss window is also reduced, particularly for flash memory cells nearing contact cells. Accordingly, it is desirable to have methods that ease buried drain contact induced operation and which also enhance the reliability of a flash memory